EE 140 HW 10
Due Wednesday 4/18/01 at 5 pm in 497 Cory

1) Create the simplest sample and hold circuit: an NMOS transistor and a capacitor (like figure 8.3 but without the unity gain amplifier).  Use W/L=1/0.5, and Chold=100fF.  Drive the analog input of the circuit with a ramp from 0 to 5 volts in 10microseconds, and drive the gate of the sampling FET with a 1MHz square wave with 100ns rise and fall times.

  1. Use transient analysis and plot the analog input, the clock signal, and the analog output.
    1. How close is the analog output to the analog input (just after the falling edge of the clock)?
    2. Is the error constant over the range of Vin?
    3. What range of voltages can NMOS switches pass?
    4. What range of voltages can PMOS switches pass?
  2. Calculate the RC time constant of this NMOS switch with an analog input of 2.5 volts.  If you need a settling time of 6 tau, what is the maximum frequency at which we can run the clock?
  3. Create the same plot as 1A, but use a W/L of 10/1.  How much charge injection do you see? What is the maximum frequency at which we could run the clock for this size sampling transistor?
  4. Create the same plot, and use a W/L of 10/1 and a rise/fall time of 0.1ns.  How much charge injection do you see?
2) Create a CMOS sample and hold circuit like in figure 8.4 (without the amplifier), including the CMOS inverter to generate not-CLK from CLK (like in figure 10.2d)
  1. Starting with W/L = 1/0.5 for the NMOS and PMOS switch transistors and rise/fall times of 100ns as above, use transient analysis to compare the sampled output to the input.  How has it improved over the simple NMOS switch?
  2. Create the same plot, but use a W/L of 10/1.  How much charge injection do you see?
  3. Create the same plot, but use a W/L of 10/1 and a rise/fall time of .  How much charge injection do you see?
3) Using any of the telescoping cascode or the folded cascode opamps from homework set 9, implement the "resettable gain circuit" from figure 10.28 with a gain of -10.
Note: I strongly encourage you to use subcircuits in separate files on your final project.  This problem would be a good place to start: put the opamp in a separate file as a subcircuit if you can.
  1. For now, you can use NMOS transistors for all of the switches.  How will that affect your input range (think carefully about this one)?  Which switches should be replaced with CMOS switches?
  2. How does the opamp input and output range affect your allowed input range (think carefully about this one too!)?
  3. How does opamp phase margin affect the performance of this circuit?  Try switching the W/L of your amplifier to get very low phase margin (like on HW9) and look at the transient plot.
  4. Use transient analysis and measure the gain.  You might want to add a sampling switch at the output of the amplifer to get a cleaner signal to look at, but choose your sampling clock carefully.
  5. Zoom in on one phi1/phi2 cycle and explain what is happening to the voltages at all of the nodes in the circuit.