Due Tuesday, 2/6, at 5pm in 497 Cory.
For all hand and spice analysis use the "140 device model" handed out
Johns & Martin problem 3.1
Use SPICE to plot both the output current and the output resistance for
the circuit above. You will need to use the expression builder.
See Richard's note on the newsgroup.
J&M problem 3.2
Assuming W/L of 100/1 and a supply voltage of 5 V, what is the maximum
value for Ibias for which all transistors in the previous problem remain
in saturation? Plot the output swing vs. bias current.
J&M problem 3.3
Assuming W/L of 100/1; a supply voltage of 5 V; a reference current of
1mA; and a 10pF load capacitor in the previous problem: use SPICE and:
plot the DC input/output relationship for the amplifier. Using a
pen, draw lines corresponding to your hand calculations for output swing
Plot the DC gain vs. VIN , the DC input bias. Using a pen, show
your hand calculations for the gain.
Using an appropriate value for the input bias (that generates high gain),
create a Bode plot of the gain of the amplifier. Use a pen and show
your hand calculation for DC gain, 3dB frequency, and unity gain frequency.
Plot the transient response to three separate sine waves: one with a frequency
ten times less than the 3dB frequency; one equal to the 3dB frequency,
and one ten time more than the 3dB frequency. Choose your input bias
and amplitude for the low frequency sine wave such that the output voltage
swing is 3V, and keep the same bias and amplitude for the successive simulations.
How well did your Bode plot predict the amplitude and phase of the transient
plot? Mark your calculations for amplitude and phase in pen on the
Carefully draw a plot of 3 equi-current lines as a function of drain
and gate voltages from 0-5V for an NMOS FET with W/L of 10/0.5, and for
100/5. (these two plots will look similar to the tube plot
from the last homework). Use currents of 20uA, 2mA, and 8mA.
Label where on each of the curves the transistor goes into saturation.
Clearly label which parts of the Vd/Vg space correspond to the device being
off, saturated, and linear. Label each of your curves with the maximum
gain at that current. How are the two plots different for the two
Design an amplifier with a low frequency gain of 100 and a unity gain frequency
of 1 GHz with a 10pF load . Use a PMOS-input common-source amplifier
with an NMOS current source. You may use one resistor in your circuit,
and assume a 5V supply, but all other devices must be FETs. Try to
minimize power dissipation in your amplifier.
Calculate the gm that you will need to meet the bandwidth spec.
Write down the resulting relationship between drain current and Veff
Write down the gain of the circuit in terms of lambda and Veff
Pick Veff, lambda, and Id consistent with the above constraints.
Calculate the corresponding W/L for the input transistor
Design the bias network.
Use spice to plot gain vs. Vin, and frequency response. Use a pen
to annotate the plot with your hand calculations.
Find the min, max, and average values for gate oxide thickness, K',
and Vt for P and N type FETs in the 0.5 micron AMI process offered through
go to www.mosis.org and select "technical support"
select "wafer test results and spice models"
You should see the AMI 0.5 um process listed. Take your data from
all of the "Txxx" runs