EE 140 HW 4
Due Tuesday 2/12/01 at 5 pm in 497 Cory

1. Calculate the operating point, small-signal parameters gm, ro, Cgs, Cdb, and Cdg for an NMOS-input common source amplifier with a PMOS load.  Assume a bias current of 400uA, and a W/L for the NMOS of 100/1 and a W/L of 200/1 for the PMOS device.
2. Calculate the total output capacitance, low frequency gain, pole frequency, unity gain frequency, zero frequency, and high-frequency gain of this amplifier.
3. Calculate the effective capacitance at the input node of the amplifier (don't forget Miller multiplication of Cgd).  How does this compare with the total output capacitance calculated above?
4. What is the pole frequency of this amplifier if it is driven by a source impedance of 25kOhm?
5. What is the pole frequency of this amplifier if it is driving a capacitance equal to its own equivalent input capacitance?
6. Draw a the magnitude portion of a Bode plot for this amplifier.  On the same graph, draw the Bode plot for the amplifier with an output load equal to its effective input capacitance.  On the same graph, draw the Bode plot of two of the basic amplifiers with an ideal unity-gain buffer between them.  On the same graph, draw the bode plot of two of the basic amplifiers cascaded together.
7. Using the models below, generate the same plots above using HSPICE.  Be very careful with your biasing when you have the two amplifiers cascaded (make sure that all transistors are in saturation).   You can create an ideal unity gain buffer using a voltage controlled voltage source in SPICE.
* these models tell spice to calculate Cgs and Cgd the same way that you do.  Spice will now (with the "capop=0")
* leave off Cdb though, so to get better matching between your hand calcs and spice you should probbaly put it into
* your spice deck by hand
.model nmos1 nmos vto=1 tox=6.9nm kp=200u lambda=0.1 gamma=0.5 phi=0.6
+ capop=0 cgdo=0.5n
.model pmos1 pmos vto=-1 tox=6.9nm kp=100u lambda=0.1 gamma=0.5 phi=0.6
+ capop=0 cgdo=0.5n