Due Tuesday 3/20/01 at 5 pm in 497 Cory

1) Consider a PMOS-input 2-stage opamp similar to the one shown in figure
5.2 in J&M.

For this exercise:

- ignore the compensation network formed by Cc and Q16,
- don't use an output stage (Q8 and Q9).
- assume that all transistors are 100/1 except Q7 which is 200/1 and Q13 which is 25/1 (quick quiz: why change Q7 and Q13?)
- assume that the input pair has a desired Vdsat of 0.2 V
- assume that the supply is +-5V

- Calculate the desired bias currents flowing in Q1 through Q7
- Calculate the gm, ro, and gain of the first and second stage.
- Choose Rb such that the supply-independent bias network (Q10-15) provides the appropriate bias voltage to Q5 and Q6.
- Design a much simpler bias network to replace Q10-15 - use only a resistor and a diode-connected PMOS transistor.
- For both the supply-independent bias network, and your simpler bias network, calculate the change in currents, Vdsats, gm, ro, and gain that would result from the supply changing from +-5 to +-2.5 as the batteries die.
- Use SPICE to verify your hand calculations for bias currents, Vdsats, gm, ro, and gain calculations. Make a table with your calcs, and SPICE's calcs. The table should have 9 columns:
- Hand calculations for the Q10-15 network with +-5V and +-2.5V
- Hand calculations for the simplified bias network with +-2.5 V (hopefully +-5V would be the same as for the Q10-15 network!)
- SPICE calculations next to each of the hand-calculated columns.
- % difference between hand calculations and SPICE calculations

- Using a 5V supply with a 10 ohm series resistance, use transient analysis in spice to determine the maximum current spike during switching. Use a 1ns rise/fall time and a 5ns pulse. What is the magnitude of the voltage spike on the digital supply?
- Hook your op-amp from problem 1 up to the same voltage supply as the digital circuit, and measure the output voltage spike due to digital supply noise. Do this for both the supply-independent bias circuit, and the simplified bias circuit.