EE 140 HW 7
Due Tuesday 3/13/01 at 5 pm in 497 Cory
Design a two stage op-amp with the following specs:
You may use 1 ideal current source in your design to set up bias voltages.
All other elements should be FETs and capacitors.
open-loop low-frequency gain of at least 1,000
open-loop low-frequency gain of at least 100 with a resistive load of 1k
60 degree phase margin (fp2 >= 2*fu) with a capacitive
load of 20 pF
+-2.5 V power supply, output swing to within 0.5V of either rail
unity gain bandwidth of 100MHz
Calculate Cc and gm, Id, and Vdsat
for the input pair and second stage input
Calculate the corresponding W/L values for all transistors
Calculate the parastic capacitances on each of the two high-impedance nodes,
and estimate their effect on your performance
Carefully draw your complete circuit and label each device with your hand-calculated
values for gm, Id, and Vdsat (you don't
need gm for the bias transistors).
Use spice (.op) to find the gm, Id, and Vdsat
values for all transistors at Vcm=0, 2, and -2 Volts, and label your plot
Use spice to plot the DC input/output function and gain at Vcm =0, 2, and
-2 volts, with and without a 1k resistive load. Label your plot with
the gain spec, and your hand-calculated value.
Use spice to plot the AC open-loop transfer function for the amplifier
with a 20pF capacitive load at Vcm=0, 2, and -2 V. Label the unity
gain frequency spec, and your hand calculated unity gain value. Label
the phase margin spec, and your hand calculated value.
Use spice to plot the transient response of your amplifier to a 20MHz square
wave over one or two periods when it's wired up as a unity-gain buffer.
Try cutting your compensation capacitor in half and re-running the simulation.
How small can your compensation capacitor get before bad things happen?