EE 140 Final Project

Due Tuesday, 5/8/01, 5pm in 497 Cory Hall

Input: Variable capacitor, Cs=1pF +/- 5%
Output: Digital value proportional to the change in capacitance

Report format

The report should be on 8.5x11 paper, stapled.  Please do not bind it, or put a fancy cover on it, or put it in a 3 ring binder.  Just a simple stapled stack of paper is fine.
There should be no spice decks or spice run output text in the report.  SPICE output plots would ideally be included as figures in-line with the text, but individual pages
inserted are acceptable.  I do not expect flowery prose, but I do expect the report to have reasonable flow (and correct spelling and grammar!).
Please use the following format for your report:


  1. Functional 4bit ADC with 10x pre-amplifier capable of 1kSample/second, 50%
  2. Each additional functional bit (up to 10 total): 5%
  3. Each additional factor of 10 in sample rate: 5%
  4. calculation of best and worst case charge injection and comparison to SPICE: 5%
  5. calculation of gain, unity gain freq, and phase margin of unity gain amplifier (during reset) and comparison to SPICE: 5%
  6. Demonstrating that these transitions still work with up to a 10% increase in supply voltage (to +/-2.75V): 10%
  7. Power consumption above 1mW cost your overall score 0.1% per microWatt (or 100% of your score if you burn a total of 2mW).
  8. Late projects will be penalized 30% if turned in by 5pm wednesday 5/9/01, and 60% if turned in by 5pm thursday 5/10/01.
Note: functionality of an n-bit ADC will be determined by showing inputs that correspond to 0...00, 0..01, 01...1, 10...0, 1...10, 1...11 (1-bit transitions at the bottom, middle, and top of the conversion range).
Note: your design is not *required* to have a 10x pre-amplifier, but if you're just shooting for basic credit you need one.